1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) structures having individual memory cells including access transistors and storage capacitors, and more particularly to a structure and fabrication method for a three dimensional, double trench memory cell including a shallow trench access transistor and a deep trench storage capacitor.
2. Description of the Prior Art
U.S. Pat. No. 4,786,954 issued Nov. 22, 1988 to Morie et al, entitled DYNAMIC RAM CELL WITH TRENCH SURROUNDED SWITCHING ELEMENT, a semiconductor memory device is described which has a semiconductor substrate of one conductivity type in which a plurality of memory cells are formed, each of the plurality of memory cells including at least one capacitor and having a trench which is formed from one major surface of the semiconductor substrate so as to surround at least one memory cell, wherein a first insulating film having element isolation properties is formed on a bottom and most areas of side wall surfaces of the trench, a first conductive film serving as one electrode of the capacitor is formed on the side wall of the first insulating film and an exposed portion of the semiconductor substrate which is not covered with the first insulating film, a second insulating film is formed on the first conductive film, and a second conductive film serving as the other electrode of the capacitor is formed on the second insulating film.
U.S. Pat. No. 4,791,463 issued Dec. 13, 1988 to Malhi, entitled STRUCTURE FOR CONTACTING DEVICES IN THREE DIMENSIONAL CIRCUITRY, discloses the fabrication of a dRAM cell which is an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the side walls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk side wall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate.
In U.S. Pat. No. 4,797,373 issued Jan. 10, 1989 to Malhi et al, entitled METHOD OF MAKING DRAM CELL WITH TRENCH CAPACITOR, a DRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate side walls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. Word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
U.S. Pat. No. 4,801,988 issued Jan. 31, 1989 to Kenney, entitled SEMICONDUCTOR TRENCH CAPACITOR CELL WITH MERGED ISOLATION AND NODE TRENCH CONSTRUCTION, discloses a semiconductor trench capacitor construction having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer formed along the upper portion of the trench side walls. The trench isolation structure facilitates larger capacitor constructions and allows the capacitors to abut adjacent capacitors and other devices.
Japanese Patent No. 63-17553 issued Jan. 25, 1980 to Ikhijima, entitled SEMICONDUCTOR MEMORY STORAGE AND ITS MANUFACTURE, describes a memory cell having fine structure by forming not only a capacitor for the memory cell but also a memory transistor on the side surface of a columnar region in a semiconductor substrate.
Japanese Patent No. 61-22665 issued Jan. 31, 1986 to Murata, entitled SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, discloses a technique to reduce the occupying area of a switching element and a capacitance element by a method wherein a small hole which is formed in the inner direction from the main surface on the main surface part of a semiconductor base plate, and a switching element and a capacitance element are buried in the small hole.
Japanese Patent No. 63-110770 dated May 16, 1988, entitled SEMICONDUCTOR DYNAMIC RAM, discloses a structure that includes a unit memory cell in a shallow trench formed in a deep trench.
European Patent Application No. 86301758.8 filed Mar. 11, 1968, entitled SEMICONDUCTOR MEMORY DEVICE, shows a MOS capacitor buried in a groove in a substrate.
In U.S. Pat. No. 4,649,625 issued Mar. 17, 1987 to Lu, entitled DYNAMIC MEMORY DEVICE HAVING A SINGLE-CRYSTAL TRANSISTOR ON A TRENCH CAPACITOR STRUCTURE AND A FABRICATION METHOD THEREFOR, dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly, a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical side walls of the trench and wherein the access transistor is isolated by insulator.
In U.S. Pat. No. 4,672,410 issued June 9, 1987 to Miura et al, entitled SEMICONDUCTOR MEMORY DEVICE WITH TRENCH SURROUNDING EACH MEMORY CELL, a semiconductor device is described that has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being constituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a side wall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a conductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the side wall surface of the trench, a gate electrode formed along the gate insulating film, and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film.
In U.S. Pat. No. 4,713,678 issued Dec. 15, 1987 to Womack et al, entitled DRAM CELL AND METHOD, a DRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench side walls. Signal charge is stored on the capacitor plate insulated from the substrate.
U.S. Pat. No. 4,728,623 issued Mar. 1, 1988 to Lu et al, entitled FABRICATION METHOD FOR FORMING A SELF-ALIGNED CONTACT WINDOW AND CONNECTION IN AN EPITAXIAL LAYER AND DEVICE STRUCTURES EMPLOYING THE METHOD, discloses a fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process.
U.S. Pat. No. 4,751,557 issued June 14, 1988 to Sunami et al, entitled DRAM WITH FET STACKED OVER CAPACITOR, describes a semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
In U.S. Pat. No. 4,769,786 issued Sep. 6, 1988 to Garnache et al, entitled TWO SQUARE MEMORY CELLS, a memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given side wall of the trench, switching means having a control element and a current carrying element disposed on the given side wall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given side wall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.